The present invention relates to a semiconductor device and a method of manufacture thereof, and more particularly to a semiconductor device including MISFETs (Metal-Insulator-Semiconductor Field Effect Transistors) and a method of manufacture thereof.
A conventional method of manufacturing MISFETs having metal gate electrodes will be described with reference to FIGS. 1A, 1B, and 1C.
First, as shown in FIG. 1A, a gate oxide layer 312 is formed on a p-type semiconductor substrate 311. Next, a polysilicon layer 313, a barrier metal layer 314 for suppressing the reaction of polysilicon and tungsten (W), and a metal layer 315 made of tungsten are deposited in sequence onto the gate oxide layer and then patterned using standard lithographic and RIE (Reactive Ion Etching) techniques to form gate electrodes. After that, p-type impurities are ion implanted into the substrate 311 using the gate electrodes as a mask to form source/drain diffusion layers 316 in the substrate.
Next, as shown in FIG. 1B, a silicon nitride layer 317 is deposited over the entire surface and then etched back by means of RIE techniques to leave a sidewall spacer of silicon nitride on the sidewall of the gate electrode.
Next, as shown in FIG. 1C, after the deposition of a silicon oxide layer 318 over the entire surface, the silicon oxide layer 318 is etched using a predetermined contact pattern to form contact holes 319.
Note here that, in this example, the contact hole adjacent to the gate electrode is not formed using a self-aligned process.
Recently, semiconductor devices having a logic section and a memory section built into the same chip are in increasing demand.
In general, the logic section requires high-performance MISFETs as compared with the memory section. To achieve high performance, it is required to lower the sheet resistance of the diffusion layers of each MISFET. This is realized by forming a layer of silicide such as TiSi.sub.2 or CoSi.sub.2.
In the memory section, the source/drain diffusion layers of the MISFETs are formed shallower than in the logic section. Thus, if a layer of silicide were formed on the diffusion layers of the MISFETs within the memory section, a spike would be produced at the bottom of the silicide layer. This would increase the possibility of being shorted to the substrate, resulting in an increase in junction leakage in the source/drain diffusion layers. It is therefore not desirable to form the layer of silicide in the MISFETs in the memory section.
However, according to conventional methods of manufacturing a semiconductor device having a logic section and a memory section built in, the addition of a process of forming a layer of silicide on the source/drain diffusion layers results in a problem that silicide is formed on the diffusion layers of both the MISFETs in the logic section and the MISFETs in the memory section and thus a structure in which no layer of silicide is existent in the memory section cannot be attained.